Selfaligned process for a flash memory

ABSTRACT

A selfaligned process for a flash memory comprises applying a solution with a high etch selectivity to etch the sidewall of the tungsten silicide in the gate structure of the flash memory during a clean process before forming a spacer for the gate structure. This process prevents the gate structure from degradation caused by thermal stress.

FIELD OF THE INVENTION

[0001] The present invention relates generally to a semiconductorprocess, and more particularly to, a selfaligned process for a flashmemory.

BACKGROUND OF THE INVENTION

[0002] In a complex integrated circuit (IC), the shrinkage of thedevices thereof makes the design more difficult. Process such asselfalignment and other techniques are used for the desired designs.

[0003]FIG. 1 shows a cross-sectional view of a gate structure 10 in atypical flash memory, in which a tunnel oxide 14 is formed on asubstrate 12 with a floating gate polysilicon layer 16 thereon, and anoxide-nitride-oxide (ONO) layer 18 is further formed on the polysiliconlayer 16 with a control gate polysilicon layer 20 thereon. Moreover, acontrol gate tungsten silicide layer 22 and a hard mask layer 24 areformed on the polysilicon layer 20, and a source 30 and a drain 32 areformed on the substrate 12. In the formation of the gate structure 10,deposition and etching processes are used to obtain a gate stack on thesubstrate 12. Then selfaligned process with the gate stack as a mask isused to form the source 30 and drain 32. After forming the spacers 26and 28, a selfaligned process is further used to form source and draincontacts. Prior arts are proposed for such selfaligned processes, suchas in U.S. Pat. Nos. 5,907,781 and 6,444,530 issued to Chen et al.

[0004] However, due to the tungsten silicide layer sandwiched in thegate structure, the critical dimension (CD) will be enlarged and thedistances between the gate and the contact windows of the source anddrain will be shortened by the thermal expansion of the tungstensilicide layer resulted from the thermal stress when the crystalstructure of the tungsten silicide is transferred from tetragon cubic tohexagon cubic in the subsequent thermal process, such as oxidation andannealing. In addition, the breakdown voltage of the structure is lowerfor the shortage of spaces therebetween. Further, the re-growth of thetungsten silicide grain squeezes each other and causes the sidewall ofthe gate structure rough and uneven, and as a result, the local electricfiled effect is enhanced and induces unpredicted discharge at sharpcorners to damage the gate structure and shorten the lifetime of theflash memory. It is therefore desired a selfaligned process to obtaingate structure having a flat sidewall for flash memories.

SUMMARY OF THE INVENTION

[0005] An object of the present invention is to provide a selfalignedprocess to reach a smoothed sidewall of the gate for a flash memory.

[0006] Another object of the present invention is to provide aselfaligned process to enhance the voltage endurance of the gatestructure for a flash memory.

[0007] In a selfaligned process for a flash memory, according to thepresent invention, a first polysilicon layer, ONO layer, secondpolysilicon layer, tungsten silicide layer and hard mask layer aredeposited on a tunnel oxide layer and etched to form a gate structure.Then the sidewall of the tungsten silicide layer is cleaned by asolution having a high etch selectivity to tungsten silicide after theformation of source and drain with the gate structure as a mask andbefore annealing process. Spacer is further formed on the sidewall ofthe gate structure, and selfaligned contact window process issubsequently preceded.

BRIEF DESCRIPTION OF DRAWINGS

[0008] These and other objects, features and advantages of the presentinvention will become apparent to those skilled in the art uponconsideration of the following description of the preferred embodimentsof the present invention taken in conjunction with the accompanyingdrawings, in which:

[0009]FIG. 1 is the cross-sectional view of the gate structure in atypical flash memory;

[0010]FIG. 2 is the cross-sectional view after forming a gate stack andsource/drain;

[0011]FIG. 3 is the cross sectional view after forming a spacer on thesidewall of the gate structure;

[0012]FIG. 4 is an illustration of a conventional gate structure afterdeformation caused by thermal expansion of the tungsten silicide in thegate structure;

[0013]FIG. 5 is a microscope photograph of a conventional gatestructure; and

[0014]FIG. 6 is a microscope photograph of the gate structure producedby the inventive process.

DETAILED DESCRIPTION OF THE INVENTION

[0015] An embodiment according to the present invention to illustrate aselfaligned process for a flash memory is shown in FIG. 2 to FIG. 3.FIG. 2 is the cross-sectional view after a gate stack 10 and a source30/drain 32 are formed, in which a tunnel oxide layer 14 is formed on asubstrate 12 with a polysilicon layer 16 thereon, an ONO layer 18 isformed on the polysilicon layer 16 with another polysilicon layer 20thereon, and a tungsten silicide layer 22 is formed on the secondpolysilicon layer 20 with a hard mask layer 24 thereon. After formingthe gate stack 10, the source 30 and drain 32 are formed on thesubstrate 12 with the gate structure 10 as the mask in the firstselfaligned process. Then a solution with a high etch selectivity totungsten silicide is used to clean the sidewall of the tungsten silicidelayer 22 in the gate structure 10. Preferably, SC-1 is used for thesolution in this clean process. SC-1 is an alkaline peroxide solutionthat composes of five parts of deionized water, one part of 30% hydrogenperoxide, and one part of 29% ammonia. After this step, the sidewall ofthe tungsten silicide layer 22 is etched for the control of the criticaldimension of the tungsten silicide layer 22. When the high etchingselectivity solution is used to clean the sidewall of the tungstensilicide layer 22, the tungsten silicide layer 22 has a faster etchingrate than other layers, and thus the sidewall of the tungsten silicidelayer 22 is etched to form recess on its sidewall.

[0016] After the above clean process is finished, rapid thermalprocessing (RTP) is preceded in an atmosphere containing oxygen radicalin a chamber so as to activate the gate, source and drain structures andform an oxide layer at the polysilicon 16 outskirt of the floating gatepolysilicon 16 to prevent current leakage. Due to the thermal treatmentusing rapid thermal treatment in an atmosphere with oxygen radical,surface reaction is the main reaction mechanism of the thermal oxidationin this atmosphere and thus the tungsten silicide layer 22 is keptsmooth on its surface and not easy to expand. When using the rapidthermal process in an atmosphere with oxygen free radical, hydrogen andoxygen are additionally pumped into the chamber at a low pressure fromabout 5 torrs to 50 torrs.

[0017] After the above annealing process, the crystal structure of thetungsten silicide layer 22 is transferred from tetragon cubic crystal tohexagon cubic crystal. SiN or SiO2 is deposited and etched to formspacers 26 and 28 on the sidewalls of the gate structure 10, as shown inFIG. 3. Since the tungsten silicide layer 22 is previously cleaned witha high etch selectivity solution, gaps 34 and 36 are formed between thetungsten silicide layer 22 and spacers 26 and 29 from the recesses, andthereby increasing the distance between the tungsten silicide layer 22and spacers 26 and 28. When the tungsten silicide layer 22 expands dueto the thermal stress in the subsequent thermal process, no squeezing ishappened to damage the gate structure 10. As a result, the surface ofthe tungsten silicide layer 22 and gate structure 10 is kept smooth, andthe distances between the tungsten silicide layer 22 and contact windowswill not be shortened. Poor performance such as increasing in localelectric field and decreasing in breakage voltage won't happen.

[0018]FIG. 4 is an illustration of the deformation of a conventionalgate structure due to the thermal expansion of the tungsten silicide forcomparison with the resultant structure formed by the inventive process.In a conventional selfaligned process, the tungsten silicide layer in agate structure will expand due to thermal stress in any subsequentthermal process. Since there is no excess space in the gate structurefor the expanded volume of the tungsten silicide layer caused by thermalstress, the grains inside the tungsten silicide layer will push eachother and increases the critical dimension of the tungsten silicidelayer, and the breakage voltage between the tungsten silicide layer andcontact windows will be lowered. In contrast, the inventive selfalignedprocess generates a buffer gaps 34 and 36 between the tungsten silicidelayer 22 and spacers 26 and 28. When the tungsten silicide layer 22expands due to thermal stress, gaps 34 and 36 buffer the expansion ofthe tungsten silicide layer 22 and thereby do not affect the structureinside the tungsten silicide layer 22.

[0019]FIG. 5 is a microscope photograph of a conventional gatestructure. The squeezing of the tungsten silicide layer due to thethermal expansion caused by thermal stress can be seen thereof, and thesurface of the sidewall is very rough. FIG. 6 is a microscope photographof the gate structure produced by the inventive process, in which thetungsten silicide layer is not squeezed due to the expansion caused bythermal stress, and the surface of the sidewall is very smooth.Comparing FIGS. 5 and 6, the selfaligned process proposed in the presentinvention has obviously improved the disadvantages of the prior gatestructure.

[0020] While the present invention has been described in conjunctionwith preferred embodiments thereof, it is evident that manyalternatives, modifications and variations will be apparent to thoseskilled in the art. Accordingly, it is intended to embrace all suchalternatives, modifications and variations that fall within the spiritand scope thereof as set forth in the appended claims.

What is claimed is:
 1. A selfaligned process for a flash memory,comprising the steps of: depositing a first polysilicon layer, ONOlayer, second polysilicon layer, a tungsten silicide and a hard masklayer in stack over a tunnel oxide layer for a gate structure having asidewall; forming a drain and source regions with said gate structure asa mask; cleaning said tungsten silicide layer with a solution having ahigh etch selectivity to said tungsten silicide; performing an annealingprocess; and forming a spacer on said sidewall.
 2. A selfaligned processaccording to claim 1, wherein said cleaning said tungsten silicide layercomprises applying an SC-1 solution to said tungsten silicide layer. 3.A selfaligned process according to claim 1, wherein said performing ananneal process comprises applying a rapid thermal treatment.
 4. Aselfaligned process for a flash memory, comprising the steps of: forminga gate stack including a metal silicide on a tunnel oxide layer; forminga drain and source regions with said gate stack as a mask; etching asidewall of said metal silicide; performing an annealing process; andforming a spacer for said gate stack.
 5. A selfaligned process accordingto claim 4, wherein said etching a sidewall of said metal silicidecomprises applying a solution having a high etch selectivity to saidmetal silicide.
 6. A selfaligned process according to claim 4, whereinsaid performing an anneal process comprises applying a rapid thermaltreatment.
 7. A selfaligned process according to claim 6, wherein saidrapid thermal treatment comprises a heating in an atmosphere containingoxygen free radicals in a chamber.
 8. A selfaligned process according toclaim 7, wherein said rapid thermal treatment comprises providing ahydrogen and oxygen gases into said chamber.
 9. A selfaligned processaccording to claim 8, wherein said reactor has a pressure of about 5 to50 torrs.